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mb39c007 2 ch dc/dc converter ic with pfm/pwm synchronous rectification cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-08228 rev. *c revised may 31, 2017 description the mb39c007 is a current mode type 2-ch annel dc/dc converter ic buil t-in voltage detection, sync hronous rectifier, and down conversion support. the device is integrat ed with a switching fet, oscillator, error amplifier, pfm/pwm c ontrol circuit, refere nce voltage source, and voltage detection circui t. the external inductor and de-coupling capacitor are needed only for the external component.mb39c007 is small, achieve a highly effective dc/dc converter in the full load range. this device is suitable as the built-in power supply for handheld equipment such as mobile phones/pda, dvds, and hdds. features high efficiency: 96 % (max) low current consumption: 30 a (at pfm/ch) output current: 800 ma/ch (max) input voltage range: 2.5 v to 5.5 v operating frequency: 2.0 mhz (typ) built-in pwm operation fixed function no flyback diode needed low dropout operation: for 100 % on duty built-in high-precision refere nce voltage generator: 1.30 v 2 % consumption current in shutdown mode: 1 a or less built-in switching fet: p-ch mos 0.3 (typ), n-ch mos 0.2 (typ) high speed for input and load transient response in the current mode over-temperature protection packaged in a compact package: qfn-24 applications flash roms mp3 players electronic dictionary devices surveillance cameras portable gps navigators dvd drives ip phones network hubs mobile phones etc.
document number: 002-08228 rev. *c page 2 of 41 mb39c007 contents description .............. ............................. ........................ 1 features ............................... ..................... ................... 1 applications ......... ............................. ........................... 1 1. pin assignment .............. ..................... ................... 3 2. pin descriptions ............. ..................... ................... 4 3. i/o pin equivalent circui t diagram ....................... 5 4. block diagram ................ ..................... ................... 6 4.1 current mode ................. ..................... ................ 7 5. function of each block . ..................... ................... 8 6. absolute maximum rating s .................. .............. 10 7. recommended operating conditions ................ 11 8. electrical characteristics ................... ................. 12 9. test circuit for m easuring typical operating characteristics .................... ..................... .............. 14 10. application notes ......... ..................... ................. 15 10.1 selection of components .................. .............. 15 10.2 output voltage setting .................... ................. 16 10.3 about conversion effici ency ........................... 17 10.4 power dissipation and heat considerations ................... ..................... .............. 17 10.5 xpor threshold voltage setting [vporh, vporl] ................. .......................... ...................... 18 10.6 transient response ..... ..................... .............. 19 10.7 board layout, design ex ample ...................... 19 11. example of standard operation characteristics.................... .................... ................ 21 11.1 characteristics ch1 ................... .......................... 21 11.2 switching waveform .... ..................... .............. 29 11.3 output waveforms at sudden load changes 30 11.4 ctl start-up waveform .. .................. .............. 31 11.5 ctl stop waveform ....... .................. .............. 33 11.6 current limitation wavefo rm .......................... 33 11.7 voltage detection wavefo rm .......................... 34 11.8 waveform of dynamic output voltage transition (vo1 1.8 v 2.5 v) ........ ................ 34 12. application circuit exam ples ........................... 35 12.1 application circuit exam ple 1 ........... .............. 35 12.2 application circuit exam ple 2 ........... .............. 36 12.3 application circuit example components list 37 13. usage precautions .......... ..................... .............. 38 14. ordering information ... ...................... ................ 38 15. rohs compliance information ......................... 38 16. package dimension ........ ..................... .............. 39 document history ................. .................... ................ 40 sales, solutions, and legal information ................. 41
document number: 002-08228 rev. *c page 3 of 41 mb39c007 1. pin assignment lx2 lx1 dgnd2 dgnd2 dgnd1 dgnd1 ctlp 19 20 21 22 23 24 12 11 10 9 8 7 123456 18 17 16 15 14 13 vref ctl2 ctl1 agnd avdd dvdd2 dvdd2 out2 mode2 vrefin2 xpor dvdd1 dvdd1 out1 mode1 vrefin1 vdet (top view) (wnn024)
document number: 002-08228 rev. *c page 4 of 41 mb39c007 2. pin descriptions pin no. pin name i/o description 1ctlpi voltage detection circuit block control input pin. (l : voltage detection function stop , h : normal operation) 2, 3 ctl2, ctl1 i dc/dc converter block control input pins. (l : shut down , h : normal operation) 4 agnd - control block ground pin. 5 avdd - control block power supply pin. 6 vref o reference voltage output pin. 7 vdet i voltage detection input pin. 8, 23 vrefin1, vrefin2 i error amplifie r (error amp) non-inverted input pins. 9, 22 mode1, mode2 i operation mode switch pins. (l : pfm/pwm mode , open : pwm mode) 10, 21 out1, out2 i output voltage feedback pins. 11, 12 dvdd1 - drive block power supply pins. 19, 20 dvdd2 13, 18 lx1, lx2 o inductor connection output pins. high impedance during shut down. 14, 15 dgnd1 - drive block ground pins. 16, 17 dgnd2 24 xpor o vdet circuit output pin. connected to an n-ch mos open drain circuit.
document number: 002-08228 rev. *c page 5 of 41 mb39c007 3. i/o pin equivalent circuit diagram gnd vdd lx1 , lx2 ? ? gnd vdd vref xpor ? gnd ? gnd vdd ctl1 , ctl2 , ctlp gnd vdd ? ? vrefin1 , vrefin2 , vdet out1 , out2 ? ? mode1 , mode2 ? gnd vdd ? * : esd protection device
document number: 002-08228 rev. *c page 6 of 41 mb39c007 4. block diagram 3 ? + ? + v in dvdd2 11, 12 19, 20 dvdd1 avdd vout1 v in xpor 5 16, 17 dgnd2 14, 15 dgnd1 agnd 4 on/off on/off on/off ctl1 out1 3 10 8 vrefin1 dac 9 1 7 mode1 vdet ctlp ctl2 out2 v in dvdd1 i out comp. error amp error amp pfm/pwm logic control 3 ? + dvdd2 i out comp. pfm/pwm logic control lx1 13 vout2 lx2 18 24 1.30 v v ref vref vrefin2 mode2 6 21 2 23 22 mode control l:pfm/pwm open:pwm mode control l:pfm/pwm open:pwm
document number: 002-08228 rev. *c page 7 of 41 mb39c007 4.1 current mode original voltage mode type : stabil ize the output voltage by comparing two items below and on-duty control. ? voltage (v c ) obtained through negative feedback of the output voltage by error amp ? reference triangular wave (v tri ) current mode type : instead of the triangular wave (v tri ), the voltage (v idet ) obtained through i-v conversi on of the sum of currents that flow in the oscillator (re ctangular wave generation circuit) and sw fet is used. stabilize the output voltage by comparing two items below and on-duty control. ? voltage (v c ) obtained through negative feedback of the output voltage by error amp ? voltage (v idet ) obtained through i-v conversion of t he sum of current that flow in the o scillator (rectangular wave generation circuit) and sw fet v in ton toff v tri vc vc v tri v in toff vc vc v idet s r ton sr-ff v idet q ? + ? + voltage mode type model current mode type model oscillator note : the above models illustrate th e general operation and an actual ope ration will be preferred in the ic.
document number: 002-08228 rev. *c page 8 of 41 mb39c007 5. function of each block pfm/pwm logic control circuit i n normal operation, frequency (2.0 mhz) which is set by the bu ilt-in oscillator (square wave os cillation circuit) controls the built-in p-ch mos fet and n-ch mos fet for the synchro nous rectification operation. in the light load mode, th e intermittent (pfm) opera tion is executed. this circuit protects against pa ss-through current caused by syn chronous rectification and agai nst reverse current caused in a non-successive operation mode. i out comparator circuit this circuit detects the current (i lx ) which flows to the external inductor from the bu ilt-in p-ch mos fet. by comparing v idet obtained through i-v conversion of peak current i pk of i lx with the error amp output, the built-in p-ch mos fet is turned off via the pfm/pwm logic control circuit. error amp phase comp ensation circuit this circuit compares the output voltage to reference voltages such as vref. this ic has a built-in phase compensation circuit that is designed to optimize th e operation of this ic. this needs neither to be consi dered nor addition of a phase compensation circuit and an ex ternal phase compensation device. vref circuit a high accuracy reference voltage is generated with bgr (bandgap refere nce) circuit. the output voltage is 1.30 v (typ). voltage detection (vdet) circuit the voltage detection circuit monitors the vdet pin voltage. normally, use the xpor pi n through pull-up with an external resist or. when the vdet pin voltage reache s 0.6 v, it reaches the h level. timing chart example : (xpor pin pulled up to v in ) protection circuit this ic has a built-in over-temperature prot ection circuit. the over-temperature protec tion circuit turns off both n-ch and p-c h switching fets when the junction temperature reaches + 135c. when the junction temperature comes down to + 110c, the switching fet is returned to the normal operation. since the pfm/pwm control circui t of this ic is in the contro l method in current mode, the cu rrent peak value is also monitored and controlled as required. v in ctlp vdet xpor v uvlo v thhpr v thlpr v uvlo : uvlo threshold voltage v thhpr , v thlpr : xpor threshold voltage
document number: 002-08228 rev. *c page 9 of 41 mb39c007 function table [1] : don't care input output ctl1 ctl2 ctlp mode ch1 function ch2 function vdet func- tion vref func- tion switching operation l [1] stopped hl l l operation stopped stopped 1.3 v output pfm/pwm mode l h stopped operation h operation l h stopped operation h l operation stopped l h stopped operation h operation hl l open operation stopped stopped pwm fixed mode l h stopped operation h operation l h stopped operation h l operation stopped l h stopped operation h operation
document number: 002-08228 rev. *c page 10 of 41 mb39c007 6. absolute maximum ratings [ 1] : see the diagram of ? example of standard operation characteristics ?. power dissipation vs. operating ambient temperature for the package power dissipation of ta from + 25c to + 85c. [2] : when mounted on a four-l ayer epoxy board of 11.7 cm 8.4 cm [3] : c is mounted on a four-layer epoxy bo ard, which has thermal via, and the ic's thermal pad is connected to the epoxy board (thermal via is 9 holes) [4] : ic is mounted on a four-l ayer epoxy board, which has no thermal via, and the ic's therma l pad is connected to the epoxy board. notes : the use of negative voltages below ? 0.3 v to the agnd, dgnd1, and dgnd2 pin may create parasitic transi stors on lsi lines, which can cause abnormal operation. this device can be damaged if the lx 1 pin and lx2 pin are short-circuited to avdd and dvdd1/dvdd2, or agnd and dgnd1/dgnd2. warning: semiconductor devices can be permanen tly damaged by appl ication of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do no t exceed these ratings. parameter symbol condition rating unit min max power supply voltage v dd avdd = dvdd1 = dvdd2 ? 0.3 + 6.0 v signal input voltage v isig out1, out2 pins ? 0.3 v dd + 0.3 v ctlp, ctl1, ctl2, mode1, mode2 pins ? 0.3 v dd + 0.3 vrefin1, vrefin2 pins ? 0.3 v dd + 0.3 vdet pin ? 0.3 v dd + 0.3 xpor pull-up voltage v ixpor xpor pin ? 0.3 + 6.0 v lx voltage v lx lx1, lx2 pins ? 0.3 v dd + 0.3 v lx peak current i pk the upper limit value of i lx1 and i lx2 -1.8a power dissipation p d ta + 25c - 3125 [1],[2],[3] mw - 1563 [1],[2],[4] ta = + 85c - 1250 [1],[2],[3] mw - 625 [1],[2],[4] operating ambient temperature ta - ? 40 + 85 c storage temperature t stg - ? 55 + 125 c
document number: 002-08228 rev. *c page 11 of 41 mb39c007 7. recommended operating conditions note : the output current from this device has a situ ation to decrease if the power supply voltage (v in ) and the dc/dc converter output voltage (v out ) differ only by a small amount. this is a result of slope compensation and will not damage this device. warning: the recommended operating conditions are required in order to ensure the no rmal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the de vice is operated within these ranges. always use semiconductor devices within their recommende d operating condition ranges . operation outside these ranges may adversely affect reliabilit y and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not repr esented on the data sheet. users considering application outside th e listed conditions are advised to c ontact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage v dd avdd = dvdd1 = dvdd2 2.5 3.7 5.5 v vrefin voltage v refin - 0.15 - 1.30 v ctl voltage v ctl ctlp, ctl1, ctl2 pins 0 - 5.0 v lx current i lx i lx1 , i lx2 -- 800 ma vref output current i rout 2.5 v avdd = dvdd1 = dvdd2 < 3.0 v -- 0.5 ma 3.0 v avdd = dvdd1 = dvdd2 5.5 v -- 1 xpor current i por --- 1ma inductor value l -- 2.2 - h
document number: 002-08228 rev. *c page 12 of 41 mb39c007 8. electrical characteristics (ta = + 25c, avdd = dvdd1 = dvdd2 = 3.7 v, vout1/vout2 setting value = 2.5 v, mode1/mode2 = 0 v) [1] : this value is not be specified. this should be used as a referenc e to support designing the circuits. parameter sym- bol pin no. condition value unit min typ max dc/dc converter block input current i refin 8, 23 vrefin = 0.15 v to 1.3 v ? 100 0 + 100 na output voltage v out 10, 21 vrefin = 0.833 v, out = ? 100 ma 2.45 2.50 2.55 v input stability line 2.5 v avdd = dvdd1 = dvdd2 5.5 v [2] --10mv load stability load ? 100 ma out ? 800 ma - - 10 mv out pin input impedance r out out = 2.0 v 0.6 1.0 1.5 m lx peak current i pk 13, 18 output shorted to gnd 0.9 1.2 1.7 a pfm/pwm switch current i msw --30-ma oscillation frequency fosc - 1.6 2.0 2.4 mhz rise delay time t pg 2, 3, 10, 21 c1/c2 = 4.7 f, out = 0 a, out1/out2 : 0 90 % v out -4580 s sw nmos-fet off voltage v noff 13, 18 -- ? 10 [1] -mv sw pmos-fet on resistance r onp lx1/lx2 = ? 100 ma - 0.30 0.48 sw nmos-fet on resistance r onn lx1/lx2 = ? 100 ma - 0.20 0.42 lx leak current i leakm 0 lx v dd [3] ? 1.0 - + 8.0 a i leakh vdd = 5.5 v, 0 lx v dd [3] ? 2.0 - + 16.0 a protection circuit block overheating protection (junction temp.) t otph -- + 120 [1] + 135 [1] + 160 [1] c t otpl + 95 [1] + 110 [1] + 125 [1] c uvlo threshold voltage v thhuv 5, 11, 12, 19, 20 - 2.17 2.30 2.43 v v thluv 2.03 2.15 2.27 v uvlo hysteresis width v hysuv - 0.08 0.15 0.25 v voltage detection circuit block xpor threshold voltage v thhpr 7 - 575 600 625 mv v thlpr 558 583 608 mv xpor hysteresis width v hyspr --17-mv xpor output voltage v ol 24 xpor = 25 a--0.1v xpor output current i oh xpor = 5.5 v - - 1.0 a
document number: 002-08228 rev. *c page 13 of 41 mb39c007 (ta = + 25c, avdd = dvdd1 = dvdd2 = 3.7 v, vout1/vout2 setting value = 2.5 v, mode1/mode2 = 0 v) [2] : the minimum value of avdd = dvdd1 = dvdd2 is the 2.5 v or v out setting value + 0.6 v, whichever is higher. [3] : the + leak at the lx1 pi n and lx2 pin includes the curr ent of the internal circuit. [4] : sum of the current flowing into t he avdd, the dvdd1, and the dvdd2 pins. [5] : current consumption based on 100% on-duty (high side fet in full on st ate). the sw fet gate drive current is not included because the device is in full on state (no switching operation) . also the load current is not included. parameter symbol pin no. condition value unit min typ max control block ctl threshold voltage v thhct 1, 2, 3 - 0.55 0.95 1.45 v v thlct - 0.40 0.80 1.30 v ctl pin input current i ictl 0 v ctlp/ctl1/ctl2 3.7 v -- 1.0 a reference voltage block vref voltage v ref 6 vref = 0 a 1.274 1.300 1.326 v vref load stability l oadref vref = ? 1.0 ma -- 20 mv general shut down power supply current i vdd1 5, 11, 12, 19, 20 ctlp/ctl1/ctl2 = 0 v, state of all circuits off [4] -- 1.0 a i vdd1h ctlp/ctl1/ctl2 = 0 v, v dd = 5.5 v, state of all circuits off [4] -- 1.0 a power supply current at dc/dc operation 1 (pfm mode) i vdd21 1. ctlp = 0 v,ctl1 = 3.7 v, ctl2 = 0 v 2. ctlp = 0 v, ctl1 = 0 v, ctl2 = 3.7 v, out = 0 a - 30 48 a i vdd22 ctlp = 0 v, ctl1/ctl2 = 3.7 v, out = 0 a - 50 80 a power supply current at dc/dc operation 2 (pwm mode) i vdd31 1. ctlp = 0 v, ctl1 = 3.7 v, ctl2 = 0 v, mode1/ mode2 = open 2. ctlp = 0 v, ctl1 = 0 v, ctl2 = 3.7 v, mode1/ mode2 = open, out = 0 a - 3.5 10.0 ma i vdd32 ctlp = 0 v, ctl1/ctl2 = 3.7 v, mode1/mode2 = open, out = 0 a - 7.0 20.0 ma power supply current (voltage detection mode) i vdd5 ctlp = 3.7 v, ctl1/ctl2 = 0 v - 15 24 a power-on invalid current i vdd 1. ctl1 = 3.7 v, ctl2 = 0 v 2. ctl1 = 0 v, ctl2 = 3.7 v, vout1/vout2 = 90 % , out = 0 a [5] - 1000 2000 a
document number: 002-08228 rev. *c page 14 of 41 mb39c007 9. test circuit for measuring typical operating characteristics note : these components are recommended base d on the operating tests authorized. tdk: tdk corporation ssm: susumu co., ltd koa: koa corporation component specification vendor part number remarks r1 1 m koa rk73g1jttd d 1 m r3-1 r3-2 20 k 150 k ssm ssm rr0816-203-d rr0816-154-d vout1/vout2 = 2.5 v setting r4 300 k ssm rr0816-304-d r5 510 k koa rk73g1jttd d 510 k r6 100 k ssm rr0816-104-d c1 4.7 f tdk c2012jb1a475k c2 4.7 f tdk c2012jb1a475k c3 0.1 f tdk c1608jb1e104k c6 0.1 f tdk c1608jb1h104k for adjusting slow start time l1 2.2 h tdk vlf4012at-2r2m vin vout1/ vout2 l1 2.2 h c1 4.7f i ou t c2 4.7 f ctl1/ctl2 mode1/mode2 vref vrefin1/vrefin2 agnd out1/out2 avdd lx1/lx2 dvdd1/dvdd2 gnd r1 1 m v dd v dd mb39c007 dgnd1/dgnd2 vdet r4 300 k r5 510 k r6 100 k c6 0.1 f sw c3 0.1 f r3-1 20 k r3-2 150 k sw vout = 2.97 vrefin
document number: 002-08228 rev. *c page 15 of 41 mb39c007 10. application notes 10.1 selection of components 10.1.1 selection of an external inductor basically it dose not need to design inductor. this ic is designed to opera te efficiently with a 2.2 h external inductor. the inductor should be rated for a saturati on current higher than the lx peak current value during normal operating conditions, and should have a minimal dc resistance. (100 m or less is recommended.) lx peak current value i pk is obtained by the following formula. l : external inductor value i out : load current v in : power supply voltage v out : output setting voltage d : on-duty to be switched ( = v out /v in ) fosc : switching frequency (2.0 mhz) for example: when v in = 3.7 v, v out = 2.5 v, i out = 0.8 a, l = 2.2 h, fosc = 2.0 mhz the maximu m peak current value i pk is obtained by the following formula. 10.1.2 i/o capacitor selection select a low equivalent series resistanc e (esr) for the vdd input capacitor to su ppress dissipation from ripple currents. also select a low equivalent series resist ance (esr) for the output capacitor. the vari ation in the inductor current causes rip ple currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied b y the esr value. the output capacitor value has a significant impact on the op erating stability of the device when used as a dc/dc converter. therefore, cypress semico nductor generally recommends a 4.7 f capacitor, or a larger capa citor value can be used if ripple voltages are not suitable. if the v in /v out voltage difference is within 0.6 v, the use of a 10 f output capacitor value is recommended. types of capacitors ceramic capacitors are effective for reducing the esr and afford smaller dc/dc converte r circuit. however, power supply functio ns as a heat generator, therefore avoid to us e capacitor with the f-temperature rating ( ? 80 % to + 20 % ) . cypress semiconductor recommends capacitors with the b-temperature rating ( 10 % to 20 % ). normal electrolytic capaci tors are not recommended due to their high esr. tantalum capacitor will reduce esr, however, it is dangerous to use because it turns into short mode when da maged. if you insis t on using a tantalum capacitor, cypress semiconduc tor recommends the type with an internal fuse. i pk = i out + v in ? v out d 1 = i out + (v in ? v out ) v out l fosc 2 2 l fosc v in i pk = i out + (v in ? v out ) v out = 0.8 a + (3.7 v ? 2.5 v) 2.5 v 0.89 a 2 l fosc v in 2 2.2 h 2.0 mhz 3.7 v
document number: 002-08228 rev. *c page 16 of 41 mb39c007 10.2 output voltage setting the output voltage v out (v out1 or v out2 ) of this ic is defined by th e voltage input to vrefin (vre fin1 or vrefin2) . supply the voltage for inputting to vrefin from an external power supply, or set the vref output by dividing it with resistors. the output voltage when the vref in voltage is set by dividing th e vref voltage with resistors is obtained by the following form ula. note : refer to ? application circuit examples ? for the an example of this circuit. although the output voltage is defined according to the di viding ratio of resistance, select the resistance value so that the current flowing through the resistance does not exceed the vref current rating (1 ma) . v out = 2.97 v refin , v refin = r2 v ref r1 + r2 (v ref = 1.30 v) r2 r1 vref vrefin vref vrefin mb39c007
document number: 002-08228 rev. *c page 17 of 41 mb39c007 10.3 about conversion efficiency t he conversion efficiency can be improved by reduci ng the loss of the dc / dc converter circuit. the total loss ( p loss ) of the dc / dc converter is roughl y divided as follows : p loss = p cont + p sw + p c p cont : control system circuit loss (the power used for this ic to operate, including the gate driving power for internal sw fets) p sw : switching loss (the loss caused during switching of the ic's internal sw fets) p c : continuity loss (the loss ca used when currents flow through the ic's internal sw fets and external circuits ) the ic's control circuit loss (p cont ) is extremely small, less than 100 mw* (with no load). as the ic contains fets which can switch fa ster with less power, the continuity loss (p c ) is more predominant as the loss during heavy-load operation than the control circuit loss (p cont ) and switching loss (p sw ) . furthermore, the continuity loss (p c ) is divided roughly into the loss by internal sw fet on-resistance and by external inductor series resistance. p c = i out 2 (rdc + d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance rdc : external inductor series resistance i out : load current the above formula indicates that it is important to reduce rdc as much as possi ble to improve efficiency by selecting component s. * : the loss in the successive operation mode. this ic suppresses the loss in order to execute the pfm operation in the low load mode (less than 100 a in no load mode). mode is cha nged by the current peak value i pk which flows into switching fet. the threshold value is about 30 ma. 10.4 power dissipation and heat considerations the ic is so efficient that no consideratio n is required in most cases. however, if the ic is used at a low power supply voltag e, heavy load, high output voltage, or high temperature, it requires further consideration for higher efficiency. the internal loss (p) is roughly ob tained from the following formula: p = i out 2 (d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance i out : output current the loss expressed by the above formula is mainly continuity loss. the internal loss includes the switching loss and the contro l circuit loss as well but they are so small compar ed to the continuity lo ss they can be ignored. in this ic with r onp greater than r onn , the larger the on-duty c ycle, the greater the loss. when assuming v in = 3.7 v, ta = + 70c, for example, r onp = 0.36 and r onn = 0.30 according to the graph ?mos fet on? resistance vs. operating am bient temperature?. the ic's in ternal loss p is 123 mw at v out = 2.5 v and i out = 0.6 a. according to the graph ?power dissipation vs. operating ambient temperature?, the power dissipation at an operating ambient temperature ta of + 70c is 300 mw and the internal loss is smaller than the power dissipation.
document number: 002-08228 rev. *c page 18 of 41 mb39c007 10.5 xpor threshold voltage setting [v porh , v porl ] set the detection voltage by appl ying voltage to the vdet pin vi a an external resistor calculat ed according to this formula. v thhpr = 0.600 v v thlpr = 0.583 v example for setting detec tion voltage to 3.7 v r3 = 510 k r4 = 100 k v porh = r3 + r4 v thhpr r4 v porl = r3 + r4 v thlpr r4 v porh = 510 k + 100 k 0.600 = 3.66 3.7 [v] 100 k v porl = 510 k + 100 k 0.583 = 3.56 3.6 [v] 100 k r4 r3 1 m vin xpor avdd mb39c007 xpor vdet
document number: 002-08228 rev. *c page 19 of 41 mb39c007 10.6 transient response normally, i out is suddenly changed while v in and v out are maintained constant, responsi veness including the response time and overshoot/undershoot voltage is checked. as this ic has built-in error amp with an optimized design, it shows good transien t response characteristics. however, if ri nging upon sudden change of t he load is high due to th e operating c onditions, add capacitor c6 (for exmple. 0.1 f). (since this capacitor c6 chan ges the start time, check the start waveform as well.) this action is not required for dac input. 10.7 board layout, design example the board layout needs to be designed to en sure the stable operation of this ic. follow the procedure below for designing the layout. arrange the input capacitor (cin) as clos e as possible to both the vdd and gnd pi ns. make a through-hole (th) near the pins of this capacito r if the board has pla nes for power and gnd. large ac currents flow between this ic and the input capacitor (cin), output capacitor (co), an d external inductor (l). group these components as close as possible to this ic to reduce the overall loop area occu pied by this group. also try to mount these components on the same surf ace and arrange wiring without through-hole wir ing. use thick, short, and straight routes to wire the net (the layout by planes is recommended.). arrange a bypass capacitor for avdd as close as possible to both the avdd and agnd pins. make a through-hole (th) near the pins of this capaci tor if the board has planes for power and gnd. the feedback wiring to the out should be wired from the voltage output pin closes t to the output capacitor (co). the out pin is extremely sensitive and should thus be kept wired away from the lx1 pin an d lx2 pin of this ic as far as possible. if applying voltage to the vrefin1/vrefin2 pins through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. also arrange them so that the gnd pin of vrefin1/vref in2 resistor is clos e to the ic's agnd pin. further, provide a gnd exclusively for th e control line so that the resistor can be connected via a path that does not car ry current. if installing a bypa ss capacitor for the vrefin, put it close to the vrefin pin. if applying voltage to the vdet pin through dividing resistors, arrange the resistors so that th e wiring can be kept as short a s possible. also arrange so that the gnd pi n of the vdet resistor is close to th e ic's agnd pin. further, provide a gnd exclusively for the control li ne so that the resistor can be connecte d via a path that does not carry current. try to make a gnd plane on the surface to wh ich this ic will be mounted. for efficien t heat dissipation wh en using the qfn-24 package, cypress semiconductor recomm ends providing a thermal via in the footprint of the thermal pad. r2 r1 vref vrefin vref vrefin1/ vrefin2 mb39c007 c6
document number: 002-08228 rev. *c page 20 of 41 mb39c007 example of arranging ic sw system parts 10.7.1 notes for circuit design the switching operation of this ic works by monitoring an d controlling the peak current wh ich, incidentally, serves as a form of short-circuit protection. however, do not leave the output short-circ uited for long periods of time. if the output is short-circuited where v in < 2.9 v, the current limit value (peak curre nt to the inductor) tends to rise. leaving in the short-circuit state, the temperature of this ic will continue rising and activate the thermal protection. once the thermal protection stops the output, the temperature of the ic will go down and oper ation will be restarted, after which the output will repeat the st arting and stopping.although this effect will not destroy the ic, the thermal exposure to the ic over prolonged hours may affect the peripherals surrounding it. cin vin gnd cin vin co co gnd vin 1pin l l feedback line feedback line avdd bypass capacitor
document number: 002-08228 rev. *c page 21 of 41 mb39c007 11. example of standard operation characteristics (following is an example of characte ristics for connection according to ? test circuit for measuring typi cal operating characteristics ?.) 11.1 characteristics ch1 50 60 70 80 90 100 1 10 100 1000 v in = 3.0 v v in = 4.2 v ta = +25c v out = 2.5 v mode = l v in = 3.7 v v in = 5.0 v 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.2 v mode = l v in = 3.7 v v in = 5.0 v 1 10 100 1000 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.8 v v in = 3.7 v v in = 5.0 v 1 10 100 1000 50 60 70 80 90 100 v in = 4.2 v ta = +25c v out = 3.3 v mode = l v in = 3.7 v v in = 5.0 v 1 10 100 1000 load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (pfm/pwm mode) conversion efficiency vs. load current (pfm/pwm mode) conversion efficiency vs. load current (pfm/pwm mode) conversion efficiency vs. load current (pfm/pwm mode)
document number: 002-08228 rev. *c page 22 of 41 mb39c007 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = +25c v out = 2.5 v mode = open v in = 3.7 v 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.2 v mode = open v in = 3.7 v v in = 5.0 v 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.8 v mode = open v in = 3.7 v v in = 5.0 v 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 4.2 v ta = +25c v in = 3.7 v v in = 5.0 v 1 10 100 1000 v out = 3.3 v mode = open load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (pwm fixed mode) conversion efficiency vs. load current (pwm fixed mode) conversion efficiency vs. load current (pwm fixed mode) conversion efficiency ( % ) conversion efficiency vs. load current (pwm fixed mode) conversion efficiency ( % ) load current i out (ma) load current i out (ma)
document number: 002-08228 rev. *c page 23 of 41 mb39c007 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.0 3.0 4.0 5.0 6.0 i out = -100 ma i out = 0 a ta = +25c v out = 2.5 v mode = l 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.0 i out = -100 ma i out = 0 a ta = +25c v out = 2.5 v mode = open 3.0 4.0 5.0 6.0 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 0 200 400 600 ta = +25c v in = 3.7 v v out = 2.5 v mode = l 800 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 0 ta = +25c 400 200 600 800 v out = 2.5 v v in = 3.7 v mode = open output voltage vs. input voltage (pwm fixed mode) output voltage v out (v) output voltage vs. input voltage (pfm/pwm mode) output voltage v out (v) input voltage v in (v) input voltage v in (v) load current i out (ma) output voltage v out (v) load current i out (ma) output voltage v out (v) output voltage vs. load current (pfm/pwm mode) output voltage vs. load current (pwm fixed mode)
document number: 002-08228 rev. *c page 24 of 41 mb39c007 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 2.0 3.0 4.0 5.0 6.0 i out = -100 ma i out = 0 a ta = +25c v out = 2.5 v 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 -50 0 +50 +100 v in = 3.7 v v out = 2.5 v i out = 0 a 0 5 10 15 20 25 30 35 40 45 50 2.0 3.0 4.0 5.0 6.0 ta = +25c v out = 2.5 v mode = l 0 1 2 3 4 5 6 7 8 9 10 ta = +25c v out = 2.5 v mode = open 2.0 3.0 4.0 5.0 6.0 input voltage v in (v) reference voltage v ref (v) input voltage v in (v) input current i in ( a) input voltage v in (v) input current i in (ma) reference voltage vs. input voltage input current vs. input voltage (pfm/pwm mode) input current vs. input voltage (pwm fixed mode) operating ambient temperature ta (c) reference voltage v ref (v) reference voltage vs. operating ambient temperature
document number: 002-08228 rev. *c page 25 of 41 mb39c007 0 5 10 15 20 25 30 35 40 45 50 -50 0 +50 +100 v in = 3.7 v v out = 2.5 v mode = l 0 1 2 3 4 5 6 7 8 9 10 v in = 3.7 v v out = 2.5 v mode = open -50 0 +50 +100 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 ta = +25c v out = 1.8 v i out = -100 ma 2.0 3.0 4.0 5.0 6.0 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 v in = 3.7 v v out = 2.5 v i out = -100 ma -50 0 +50 +100 power supply voltage v in (v) oscillation frequency f osc (mhz) operating ambient temperature ta (c) oscillation frequency f osc (mhz) oscillation frequency vs. power supply voltage oscillation frequency vs. operating ambient temperature operating ambient temperature ta (c) input current i in ( a) input current vs. operating ambient temperature (pfm/pwm mode) operating ambient temperature ta (c ) input current i in (ma) i nput current vs. operat ing ambient temperature (pwm fixed mode)
document number: 002-08228 rev. *c page 26 of 41 mb39c007 0 0.1 0.2 0.3 0.4 0.5 0.6 ta = +25c p-ch n-ch 2.0 3.0 4.0 5.0 6.0 0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 3.7 v v in = 5.5 v -50 0 +50 +100 0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 3.7 v v in = 5.5 v -50 0 +50 +100 operating ambient temperature ta ( c) n-ch mos fet on resistor r onn ( ) n-ch mos fet on resistor vs. operating ambient temperature input voltage v in (v) mos fet on resistor r on ( ) mos fet on resistor vs. input voltage operating ambient temperature ta (c) p-ch mos fet on resistor r onp ( ) p-ch mos fet on resistor vs. operating ambient temperature
document number: 002-08228 rev. *c page 27 of 41 mb39c007 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ta = +25c v out = 2.5 v v thlm d v thm m d 2.0 3.0 4.0 5.0 6.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ta = +25c v out = 2.5 v v thhct v thlct 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 ta = +25c v porh v porl 2.0 3.0 4.0 5.0 6.0 input voltage v in (v) v xpor (v) v xpor vs. input voltage input voltage v in (v) mode v th (v) mode v th vs. input voltage input voltage v in (v) ctl v th (v) ctl v th vs. input voltage v thhct : circuit off on v thlct : circuit on off
document number: 002-08228 rev. *c page 28 of 41 mb39c007 0 500 1000 1500 2000 2500 3000 3500 +85 -50 0 +50 +100 1250 3125 0 500 1000 1500 2000 2500 3000 3500 1563 +85 625 -50 0 +50 +100 operating ambient temperature ta (c) power dissipation p d (mw) power dissipation vs. operating ambient temperature (with thermal via) operating ambient temperature ta (c) power dissipation p d (mw) power dissipation vs. operating ambient temperature (without thermal via)
document number: 002-08228 rev. *c page 29 of 41 mb39c007 11.2 switching waveform 2 s/div v o1 : 20 mv/div (ac) v lx1 : 2.0 v/div l lx1 : 500 ma/div v in = 3.7 v, i o1 = ? 5 ma, v o1 = 2.5 v, mode = l ,ta = + 25 c 1 2 4 2 s/div v o2 : 20 mv/div (ac) v lx2 : 2.0 v/div l lx2 : 500 ma/div 1 2 4 v in = 3.7 v, i o2 = ? 5 ma, v o2 = 1.8 v, mode = l ,ta = + 25 c 2 s/div v o1 : 20 mv/div (ac) v lx1 : 2.0 v/div l lx1 : 500 ma/div 1 2 4 v in = 3.7 v, v o1 = 2.5 v, i o1 = ? 800 ma, mode = l ,ta = + 25 c 2 s/div v o2 : 20 mv/div(ac) v lx2 : 2.0 v/div l lx2 : 500 ma/div 2 4 1 v in = 3.7 v, v o2 = 1.8 v, i o2 = ? 800 ma, mode = l ,ta = + 25 c pfm/pwm operation pwm operation
document number: 002-08228 rev. *c page 30 of 41 mb39c007 11.3 output waveforms at sudden load changes 100 s/div v o1 : 200 mv/div v lx1 : 2.0 v/div l o1 : 1 a/div 0 a ? 800 ma 1 2 4 v in = 3.7 v, v o1 = 2.5 v, mode = l ,ta = + 25 c 100 s/div v o2 : 200 mv/div v lx2 : 2.0 v/div l o2 : 1 a/div 0 a ? 800 ma 1 2 4 v in = 3.7 v, v o2 = 1.8 v, mode = l ,ta = + 25 c 20 ma 800 ma 100 s/div v o1 : 200 mv/div v lx1 : 2.0 v/div l o1 : 1 a/div 4 2 1 v in = 3.7 v, v o1 = 2.5 v, mode = l ,ta = + 25 c v lx2 : 2.0 v/div v o2 : 200 mv/div l o2 : 1 a/div 100 s/div 20 ma 800 ma 1 2 4 v in = 3.7 v, v o2 = 1.8 v, mode = l ,ta = + 25 c v lx1 : 2.0 v/div l o1 : 1 a/div 100 ma 800 ma 100 s/div v o1 : 200 mv/div 1 2 4 v in = 3.7 v, v o1 = 2.5 v, mode = l ,ta = + 25 c v lx2 : 2.0 v/div l o2 : 1 a/div 100 ma 800 ma v o2 : 200 mv/div 100 s/div 1 2 4 v in = 3.7 v, v o2 = 1.8 v, mode = l ,ta = + 25 c 0 a ? 800 ma ? 20 ma ? 800 ma ? 100 ma ? 800 ma
document number: 002-08228 rev. *c page 31 of 41 mb39c007 11.4 ctl start-up waveform v lx1 : 5 v/div ctl1 : 5 v/div i lx1 : 1 a/div v in = 3.7 v, v o1 = 2.5 v, mode = l, ta = + 25 c 10 s/div v o1 : 1 v/div 2 4 1 3 ctl2 : 5 v/div v o2 : 1 v/div v lx2 : 5 v/div i lx2 : 1 a/div 10 s/div v in = 3.7 v, v o2 = 1.8 v, mode = l, ta = + 25 c 3 4 2 1 i lx1 : 1 a/div v lx1 : 5 v/div v o1 : 1 v/div ctl1 : 5 v/div 10 s/div v in = 3.7 v, v o1 = 2.5 v , i o1 = ? 800 ma , mode = l, ta = + 25 c 2 4 1 3 10 s/div v in = 3.7 v, v o2 = 1.8 v , i o2 = ? 800 ma , mode = l, ta = + 25 c 4 2 1 ctl2 : 5 v/div v o2 : 1 v/div v lx2 : 5 v/div 3 i lx2 : 1 a/div no load, no vrefin capacitor maximum load, no vrefin capacitor
document number: 002-08228 rev. *c page 32 of 41 mb39c007 v in = 3.7 v, v o1 = 2.5 v , mode = l, ta = + 25 c 4 2 1 3 i lx1 : 1 a/div v o1 : 1 v/div ctl1 : 5 v/div v lx1 : 5 v/div 1 ms/div v in = 3.7 v, v o2 = 1.8 v , mode = l, ta = + 25 c 4 2 1 3 i lx2 : 1 a/div v o2 : 1 v/div ctl2 : 5 v/div v lx2 : 5 v/div 1 ms/div 4 2 1 3 v in = 3.7 v, v o1 = 2.5 v , i o1 = ? 800 ma , mode = l, ta = + 25 c ctl1 : 5 v/div v o1 : 1 v/div i lx1 : 1 a/div v lx1 : 5 v/div 1 ms/div 4 2 1 3 ctl2 : 5 v/div v o2 : 1 v/div v lx2 : 5 v/div i lx2 : 1 a/div 1 ms/div v in = 3.7 v, v o2 = 1.8 v , i o2 = ? 800 ma , mode = l, ta = + 25 c no load, vrefin capacitor = 0.1 f maximum load, vrefin capacitor = 0.1 f
document number: 002-08228 rev. *c page 33 of 41 mb39c007 11.5 ctl stop waveform 11.6 current limitation waveform 1 2 3 4 ctl1 : 5 v / div 10 s / div v o1 : 1 v / div v lx1 : 5 v / div v in = 3.7 v, v o1 = 2.5 v , i o1 = ? 800 ma , mode = l, ta = + 25 c i lx1 : 1 a / div 1 2 3 4 ctl2 : 5 v / div 10 s / div v o2 : 1 v / div v lx2 : 5 v / div i lx2 : 1 a / div v in = 3.7 v, v o2 = 1.8 v , i o2 = ? 800 ma , mode = l, ta = + 25 c maximum load, vrefin capacitor = 0.1 f 1 4 100 s / div v o1 : 1 v / div 1.5 a i lx1 : 1 a / div v in = 3.7 v , v o1 = 2.5 v , mode = open , ta = + 25 c 600 ma 1 4 100 s / div v o2 : 1 v / div 1.5 a i lx2 : 1 a / div v in = 3.7 v , v o2 = 1.8 v , mode = open , ta = + 25 c 600 ma
document number: 002-08228 rev. *c page 34 of 41 mb39c007 11.7 voltage detection waveform 11.8 waveform of dynamic output voltage transition (v o1 1.8 v 2.5 v) 3 1 2 v in : 3 v / div v vdet : 1 v / div v xpor : 3 v / div v in = 3.7 v , ctlp = v in , ta = + 25 c 1 ms / div pull-up xpor to v in at 1 k . 1.8 v 1 3 v o1 : 200 mv / div v vrefin1 : 200 mv / div v in = 3.7 v , l o1 = ? 800 ma , ? 576 ma ( 3.125 ) , mode = l , ta = + 25 c , no vrefin capacitor 10 s / div 2.5 v 840 mv 610 mv 1.8 v
document number: 002-08228 rev. *c page 35 of 41 mb39c007 12. application circuit examples 12.1 application circuit example 1 an external voltage is input to the reference voltage external input (vrefin1, vrefin2) , and the v out voltage is set to 2.97 times the v out setting gain. v in cpu v out1 dac1 l1 2.2 h l2 2.2 h 4.7 f c1 4.7 f c2 mb39c007 c3 4.7 f 4.7 f ctl1 mode1 vrefin1 out1 xpor lx1 dvdd1 r8 1 m r7 1 m ctl2 mode2 vref vrefin2 vdet ctlp dvdd2 dgnd1 dgnd2 c4 0.1 f c5 avdd agnd out2 lx2 dac2 apli2 v out2 v out = 2.97 v refin 3 8 2 23 9 22 6 7 1 24 21 18 10 13 4 5 16 17 19 20 14 15 11 12 apli1 l = pfm/pwm open = pwm
document number: 002-08228 rev. *c page 36 of 41 mb39c007 12.2 application circuit example 2 the voltage of vref pin is input to the reference voltage external in put (vrefin1, vrefin2) by dividing resistors. the v out1 voltage is set to 2.5 v and v out2 voltage is set to 1.8 v. r8 1 m r6 300 k r2 r5 ( 13 k + 330 k ) 343 k r1 ( 13 k + 150 k ) 163 k 300 k r7 1 m cpu mb39c0007 ctl1 vref vrefin1 ctl2 mode2 mode1 vrefin2 ctlp 3 8 2 23 6 9 22 7 1 v in c3 4.7 f 4.7 f dvdd1 dvdd2 dgnd1 dgnd2 c4 0.1 f c5 avdd agnd 4 5 16 17 19 20 14 15 11 12 out1 xpor lx1 out2 lx2 v out1 l1 2.2 h l2 2.2 h 4.7 f c1 4.7 f c2 apli2 v out2 24 21 18 10 13 apli1 v out1 = 2.97 v refin1 ( v ref = 1.30 v ) v ref v refin1 = r2 r1 + r2 1.30 v = 2.5 v v out1 = 2.97 300 k 163 k + 300 k 1.30 v = 1.8 v v out2 = 2.97 300 k 343 k + 300 k vdet l = pfm/pwm open = pwm
document number: 002-08228 rev. *c page 37 of 41 mb39c007 12.3 application circuit example components list tdk : tdk corporation fdk : fdk corporation koa : koa corporation component item part number specification package vendor l1 inductor vlf4012at-2r2m 2.2 h, rdc = 76 m smd tdk mipw3226d2r2m 2.2 h, rdc = 100 m smd fdk l2 inductor vlf4012at-2r2m 2.2 h, rdc = 76 m smd tdk mipw3226d2r2m 2.2 h, rdc = 100 m smd fdk c1 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c2 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c3 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c4 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c5 ceramic capacitor c1608jb1e104k 0.1 f (50 v) 2012 tdk r1 resistor rk73g1jttd d 13 k rk73g1jttd d 150 k 13 k 150 k 1608 1608 koa koa r2 resistor rk73g1jttd d 300 k 300 k 1608 koa r5 resistor rk73g1jttd d 13 k rk73g1jttd d 330 k 13 k 330 k 1608 1608 koa koa r6 resistor rk73g1jttd d 300 k 300 k 1608 koa r7 resistor rk73g1jttd d 1 m 1 m 0.5 % 1608 koa r8 resistor rk73g1jttd d 1 m 1 m 0.5 % 1608 koa
document number: 002-08228 rev. *c page 38 of 41 mb39c007 13. usage precautions 1. do not configure the ic over the maximum ratings if the lc is used over the maximum ratings, the lsl may be permanently damaged.it is preferable for the device to normally oper ate within the recommended usage conditions. usage outside of these cond itions adversely affect the reliability of the lsi. 2. use the devices within r ecommended operating conditions the recommended operating conditions are the conditions u nder which the lsl is guaranteed to operate.the electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the con- ditions stated for each item. 3. printed circuit board ground lines should be set up with consideration for common impedance 4. take appropriate static electricity measures containers for semiconductor materials should have anti-static protection or be made of conductive material. after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. work platforms, tools, and instruments should be properly grounded. working personnel should be grou nded with resistance of 250 k to 1 m between body and ground. 5. do not apply negative voltages the use of negative voltages below ? 0.3 v may create parasitic tr ansistors on lsi lines, whic h can cause abnormal operation. 14. ordering information 15. rohs compliance information the lsi products of cypress semiconductor with ?e1? are co mpliant with rohs directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (p bb) , and polybrominated diphenyl ethers (pbde). a product whose part number has trailing characters ?e1? is rohs compliant. part number package remarks MB39C007WQN 24-pin plastic qfn (wnn024) ?
document number: 002-08228 rev. *c page 39 of 41 mb39c007 16. package dimension dimensions nom. min. b e 2.60 bsc 4.00 bsc d a 1 a 4.00 bsc 0.00 symbol max. 0.80 0.05 0.50 bsc l 0.20 0.25 0.30 e d 2 2 2.60 bsc e c 0.35 ref 0.40 0.35 0.45 2. dimensioning and tolerancinc conforms to asme y14.5-1994. 3. n is the total number of terminals. 4. dimension "b" applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip.if the terminal has the optional radius on the other end of the terminal. the dimension "b"should not be measured in that radius area. 5. nd refer to the number of terminals on d or e side. 6. max. package warpage is 0.05mm. 1. all dimensions are in millimeters. 7. maximum allowable burrs is 0.076mm in all directions. 8. pin #1 id on top will be located within indicated zone. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. note 10. jedec specification no. ref : n/a side view bottom view top view d a e b 0.10 c 2x 0.20 c a a1 0.05 c c seating plane d2 e2 0.15 c a b 0.15 c a b 1 e b 0.05 c a b 0.20 c (nd-1) e index mark 8 4 5 9 l 9 0.10 c 2x 6 7 12 18 13 24 19 package code: wnn024 002-15158 rev. **
document number: 002-08228 rev. *c page 40 of 41 mb39c007 document history spansion publication number: ds04-27246-3e document title: mb39c007, 2 ch dc/dc conver ter ic with pfm/pwm synchronous rectification document number: 002-08228 revision ecn orig. of change submission date description of change ** ? taoa 01/07/2011 migrated to cypress and assigned document number 002-08228. no change to document contents or format. *a 5186809 taoa 03/23/2016 updated to cypress template *b 5633424 hixt 02/16/2017 updated pin assignment : change the package name from lcc-24p-m10 to wnn024 updated ordering information : change the package name from lcc-24p-m10 to wnn024 deleted ?marking format (lead free version)? deleted ?labeling sample (lead free version)? deleted ?evaluation board specification? deleted ?ev board ordering information? updated package dimension : updated to cypress format *c 5756336 masg 05/31/2017 updated to cypress template
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